Currently, programmable logic arrays (“PLAs”) provide micro-operation information for short instruction flows of usually four or less micro-operations while a micro-operation read only memory (“ROM”) is used to provide micro-operation information for long instruction flows of more than four micro-operations. This is accomplished in the processor by using a traditional decoder to decode the instructions and a trace cache to hold the short instructions and a micro-operation ROM to store the long instructions. Unfortunately, processor efficiency suffers on long instructions because of the processor switch to the slower UROM to access the long instructions. In addition, making changes to improve the access speed of one memory usually results in decreasing the access speed of the other memory. As a result, there is a large penalty (also referred to as “pipeline bubbles”) for switching from one instruction source to the other, for example, from the trace cache to the micro-operation ROM. If they were unified, there would be no penalty. An inherent benefit to using a single structure to store all of the instructions is to reduce the hardware complexity. Having a single storage structure results in less hardware to design, less potential speedpaths, etc.
Therefore, it would be advantageous to have all micro-operation information come from a single structure.